1. Field of the Invention
This invention relates generally to phase lock loops, and more particularly to an all-digital phase-domain phase-lock loop (PLL) that employs a hybrid of predictive and closed-loop architectures.
2. Description of the Prior Art
Open-loop modulation techniques for data transmission are well-known in the prior art, and exhibit undesirable frequency wander and drift Feed forward, closed-loop modulation techniques with phased-lock loop compensation for data transmission are also well known in the prior art. These closed-loop solutions use an analog compensation that is only approximate because of component matching difficulties and disagreement between the transfer functions.
The idea of phase compensating a phase locked loop (PLL) by digitally integrating the transmit modulating data bits and using the integrator output to shift the phase of the reference clock signal, while the Gaussian filtered data directly frequency modulates the VCO has been disclosed by M. Bopp et al., xe2x80x9cA DECT transceiver chip set using SiGe technology,xe2x80x9d Proc. of IEEE Solid-State Circuits Conf., sec. MP4.2, pp. 68-69, 447, February 1999. This approach however, is rather analog in nature and therefore requires precise component matching, of not only the VCO, but also the phase shifter.
A similar feed-forward compensation method which also requires a precise knowledge of the ever-changing model of the VCO and other analog circuits has been disclosed by B. Zhang, P. Allen, xe2x80x9cFeed-forward compensated high switching speed digital phase-locked loop fluency synthesizer,xe2x80x9d Proc. Of IEEE Symposium on Circuits and Systems, vol. 4, pp. 371-374, 1999.
In view of the foregoing, it is highly desirable to have a digitally-intensive PLL architecture that is compatible with modern CMOS technology in order to reduce parameter variability generally associated with analog circuits.
The present invention is directed to a hybrid of a predictive and closed-loop PLL technique and its most preferred application to implement a direct oscillator transmit modulation. An all-digital type-I PLL loop includes a digitally-controlled oscillator (DCO) where the DCO control and resulting phase error measurements are in numerical format. The current gain of the DCO is easily predicted by simply observing the past phase error responses to the DCO. With a good estimate of the current oscillator gain, normal DCO control can then be augmented with the xe2x80x9copen loopxe2x80x9d instantaneous frequency jump estimate of the new frequency control word command. The resulting phase error is expected to be very small and subject to the normal closed PLL loop correction transients.
According to one embodiment, a digital phase-locked loop with a modulation circuit comprises:
a digital phase-locked loop having a phase detector, a loop filter and a digitally-controlled oscillator (DCO), wherein the DCO is responsive to an oscillator tuning word (OTW) to generate a DCO output clock, and further wherein the phase detector is responsive to a channel selection signal, a modulating data signal and the output clock generated by the DCO to generate a phase detector output signal, and further wherein the loop filter generates a filtered phase error in response to the output signal generated by the phase detector; and
a direct modulator operational in response to the filtered phase error and the modulating signal to generate the OTW.
According to another embodiment, a phase-locked loop with a modulation circuit comprises:
a digitally-controlled oscillator responsive to an oscillator tuning word (OTW) to generate an oscillator output clock;
a direct modulator operational in response to a modulating signal and a filtered phase error to generate the OTW; and
an accumulator circuit operational in response to a frequency division ratio command, the modulating data signal and clock edge counts associated with the oscillator output clock to generate the phase error.
According to still another embodiment of the present invention, a digital phase-domain phase-locked loop circuit comprises:
a digitally-controlled oscillator (DCO);
a gain element feeding the DCO and operational to compensate DCO gain in response to a loop gain signal such that the DCO gain will have substantially no effect on loop behavior;
an oscillator phase accumulator operational to accumulate DCO generated clock edges;
a reference phase accumulator operational to accumulate a frequency division ratio command and a modulating data signal and to generate an accumulated frequency control word (FCW) therefrom;
a phase detector operational to compare the accumulated FCW and the accumulated DCO generated clock edges and generate a phase error in response thereto; and
a direct modulator operational in response to the modulating data signal and the phase error to generate the loop gain signal.
According to still another embodiment of the present invention, a method of operating a phase-locked loop having a digitally-controlled oscillator comprises the steps of:
(a) providing a phase-locked loop including a digitally-controlled oscillator (DCO) having a gain KDCO, a phase detector, and a loop filter, wherein the DCO is responsive to an oscillator tuning word (OTW) to generate a DCO output clock having a frequency fv, and further wherein the phase detector is responsive to a channel selection signal, a modulating data signal and the output clock to generate a phase detector output signal and further wherein the loop filter generates a filtered phase error in response to the phase detector output signal;
(b) providing a direct modulator operational in response to the filtered phase error and the modulating data signal to generate the OTW;
(c) communicating a channel selection signal to the phase detector and simultaneously communicating a calibration modulating data signal to both the phase detector and the direct modulator, and observing a change xcex94xcfx86 in the phase detector output signal in response to a given change xcex94x in the OTW; and
(d) estimating a DCO gain {circumflex over (K)}DCO, defined by             K      ^        DC0    =            Δφ              Δ        ⁢                  xe2x80x83                ⁢        x              ·          f      ref      
xe2x80x83such that the DCO gain KDCO can be compensated to substantially remove its effects on loop behavior.
In one aspect of the invention, a hybrid of predictive and closed PLL loop techniques is used to estimate and compensate for the gain of a DCO.
In another aspect of the invention a hybrid of predictive and closed PLL loop techniques is used to minimize undesirable parameter variability normally associated with analog circuits.
In yet another aspect of the invention, a hybrid of predictive and closed PLL loop techniques is used to directly implement oscillator frequency/phase transmit modulation to minimize system transmitter requirements.
In still another aspect of the invention, a hybrid of predictive and closed PLL loop techniques is used to implement an all-digital phase-domain PLL frequency synthesizer that accommodates the xe2x80x9cBLUETOOTHxe2x80x9d standard.
In still another aspect of the invention, a hybrid of predictive and closed PLL loop techniques employs fractional phase error correction such that a digitally-controlled oscillator gain can be compensated to substantially remove its effects on PLL loop behavior.